A Note on the IEEE Verilog Simulation Cycle

David M. Russinoff


The IEEE Verilog Standard contains a number of ambiguities and inconsistencies with respect to the semantics of event scheduling, creating difficulties for the programmer in predicting the behavior of a compliant simulator. In this note, we bring some of these issues to light and attempt to resolve them by outlining an abstract formulation of the Verilog simulation cycle, aimed at clarifying the intent of the Verilog Standard Committee. We also observe that the degree of freedom allowed by the Standard in the interleaving of concurrent processes is impractical, and if fully exercised, would inevitably lead to race conditions and unpredicable results. Consequently, this aspect of the specification has been essentially ignored by tacit agreement between implementors and users. As a remedy, we propose to modify the specification of the simulation cycle by imposing a simple restriction on the nondeterministic selection of active events. The suggested restriction would allow the programmer to eliminate race conditions without inhibiting compiler optimization.

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